M.Sc Electronics Semester III Exam Oct/Nov 2019 Shivaji University Kolhapur
The CPLD is based on _____ architecture
(a) sum-of-product
(b) product-of-sum
(c) both a and b
(d) logic block
The operator NAND and NOR are not ______
(a) cumulative
(b) associative
(c) distributive
(d) all of these
The package std_logic_1164 is accessed by ____ clause.
(a) Library
(b) use
(c) type
(d) both a and b
The VHDL is utilized for ____ design
(a) analog
(b) digital
(c) combinational
(d) digital + analog
The maning of ‘L’ is ____ in Data types STD_LOGIC_1164
(a) high
(b) 1
(c) weak 0
(d) All of these
The mode of parts in _____ declaration are five types.
(a) archtecture
(b) identity
(c) entity
(d) operators
The PLD devices are utilized for ____ circuit design
(a) analog
(b) digital
(c) combinational
(d) digital + analog
The component declaration declares the ___ of the component.
(a) name
(b) interface
(c) use
(d) both a and b
The ‘&’ operator is ____ operator used in VHDL code
(a) adding
(b) relational
(c) attaching
(d) miscellaneous
The VHDL is ____ description language.
(a) software
(b) hardware
(c) both a and b
(d) logic
The LOOP statement is used to iterate through the set of ____ statement.
(a) sequential
(b) concurrent
(c) both a and b
(d) mixed
The WAIT statement is a ______ statement.
(a) sequential
(b) concurrent
(c) both a and b
(d) mixed
The exit and next statements are used ____ loop statement.
(a) outside
(b) inside
(c) both a and b
(d) before
The front end design is used to create ______ source of desgin
(a) technology
(b) physical
(c) logic
(d) circuit
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