Solapur University M.Sc Electronic Science Sem I Paper March 2019
Solapur University M.Sc Electronic Science Previous Year Question Paper 2019 (March-April) on Digital Electronics & VHDL
| M.Sc. (Semester-II) (CBCS) Examination March/ April – 2019
Electronic Science DIGITAL ELECTRONICS AND VHDL |
|
| 1 | The following TTL sub – family is having maximum speed_________.
a) Standard TTL b) Schottky clamped TTL c) High speed TTL d) Low power TTL |
| 2 | How many flip – flops are used in master slave flip – flop?
a) 3 b) 1 c) 2 d) 4 |
| 3 | Open collector gates have ______switching times.
a) Faster b) Slower c) Medium d) None of these |
| 4 | A PLA can be used________.
a) To realize a sequential logic b) As a memory c) To realize a combinational logic d) None of these |
| 5 | The output of Moore machines is the function of________.
a) Next State b) Present State c) Present State and Present Input d) Present state and next state |
| 6 | To seriously shift a byte of data into a shift register there must be________.
a) One clock pulse b) Four clock pulse c) Eight clock pulse d) One clock pulse for each 1 in the data |
| 7 | State reduction gives _______.
a) Reduction in number of flip – flops b) Number of flip – flops remain same c) Either a) or b) d) None of the above |
| 8 | A divide by 20 ring counter requires a minimum of_______.
a) Twenty flip – flops b) Eight fli8p –flop c) Five flip- flop d) None of these |
| 9 | In PLA _____.
a) Both AND and OR matrix are programmable b) AND array is fixed and OR is programmable c) AND is programmable OR is fixed d) None of these |
| 10 | Flip – Flops can be used to make_______.
a) Latches b) Bounces – elimination switches c) Registers d) All of the above |
| 11 | The figure of merit of a logic family is given by _______.
a) Gain – bandwidth product b) Product of propogation delay time and power dissipation c) Product of fan – out d) None of these |
| 12 | A sequential circuit is one, whose output depends on _______.
a) Present State b) Present Input c) Both A) and B) d) None of these |
| 13 | Which of the following is standardized as IEEE 1364?
a) C b) C++ c) FORTRAN d) Verilog |
| 14 | How many clock pulses will be required to completely load serially a 5- bit shift register?
a) 2 b) 3 c) 4 d) 5 |
| Data Collected By – J. Jayalakshmi | |
| Published On – 5th Dec 2021 | |
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