Solapur-University-M.Sc. – Electronics (Semester-III)-2019-On Advanced Digital Design With VHDL
| Sr. No | Questions with multiple options |
| 1. | The______ are the programming technologies used for PLD.
(a) SRAM (b) EPROM (c) Flash (d) All of these |
| 2. | The FPGA architecture are based on _______ to generate logic functions.
(a) LUT (b) Multiplexer (c) Macrocell (d) Both a & b |
| 3. | The VHDL supports ____ design methodology
(a) Top-down (b) Bottom-up (c) Mixed (d) All of these |
| 4. | The generate statement is _____ statement
(a) Sequential (b) Concurrent (c) Process (d) All of these |
| 5. | The _______ adding operator used in VHDL
(a) ‘+’ (b) ‘_‘ (c) ‘&’ (d) All of these |
| 6. | The meaning of ‘H’ is ______ in Data Types sTD_LOGIC_1164
(a) High (b) 1 (c) Weak 1 (d) All of these |
| 7. | The GENERIC statement is declared in _____ of the VHDL code.
(a) Architecture (b) Entity (c) Process (d) All of these |
| 8. | The mode of ports in entity declaration are ____ types.
(a) 2 (b) 3 (c) 4 (d) 5 |
| 9. | The _____ statement provides an alternate way to suspend the execution of a process.
(a) Wait (b) Loop (c) Generate (d) Halt |
| 10. | The ____ is one of the way of design entry in the CAD process.
(a) HDL (b) VHDL (c) Verilog (d) All of these |
| 11. | The generic and constant values are assigned by _____ assignment operator.
(a) <= (b) := (c) =: (d) => |
| 12. | The extended identifier is a sequence of character written between two _____
(a) Under score (b) Forward slashes (c) Back slashes (d) Hash |
| 13. | The back end design is used to create ____ source of design.
(a) Technology (b) Physical (c) Logic (d) Circuit |
| 14. | The exit and next statements are used ____ loop statement
(a) Outside (b) Inside (c) Both a & b (d) Before |
| Data Collected By – K. Jeyanthi | |
| Published on -15th Nov 2021 | |
Leave a Reply