Solapur-University-M.Sc. – Electronics (Semester-III)-2019-On CMOS Design Technologies
| Sr. No | Questions with multiple options |
| 1. | Twin tube process uses epi layer as protection against ____
(a) Minority carriers (b) Power disscipation (c) Latchup (d) All of these |
| 2. | The cell at the bottom of the hierarchy is called as ______
(a) Root cell (b) Leaf cell (c) Composition cell (d) All of these |
| 3. | Material used for local interconnect layer is ______
(a) Polysilicon (b) Single crystal silicon (c) Sapphire (d) Silicide |
| 4. | Rise time is the time for a waveform to rise from ____ of its steady state value.
(a) 10% to 90% (b) 90% to 50% (c) 0% to 10% (d) 10% to 20% |
| 5. | Latchup results in ____
(a) Power down of circuit (b) Failure of circuit (c) Parasitic effect (d) All of these |
| 6. | As temperature increases carrier mobility ______
(a) Remains constant (b) Increases (c) Decreases (d) None of these |
| 7. | The design environments with greatest abstraction are at ____
(a) System level (b) Algorithm level (c) Both a and b (d) Component level |
| 8. | _____ power dissipation occurs due to charging and discharging of load current.
(a) Total (b) Dynamic (c) Static (d) Short circuit |
| 9. | The most popular algorithm level environment is ____
(a) PMS (b) Pseudo-layout (c) Flowcharting (d) Schematic |
| 10. | ______ process arranges bocks of a layout design to minimize area and maximize speed.
(a) Placement (b) Floor planning (c) Routing (d) None of these |
| 11. | N-plus guard ring if implemented in structure must be tide to _____
(a) VDD (b) VSS (c) n-well (d) p-well |
| 12. | Silicon in its intrinsic state is a ____
(a) conductor (b) semiconductor (c) resistor (d) none of these |
| 13. | ______ method is used to reduce bird’s beak.
(a) LOCOS (b) Czochralski (c) SWAMI (d) None of these |
| 14. | SOI uses ____ as basic substrate material.
(a) p-type substrate (b) n-type substrate (c) sapphire (d) none of these |
| Data Collected By – K. Jeyanthi | |
| Published On – 17th Nov 2021 | |
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