TN TRB PG Assistant Rescheduled Exam Date 2022 | TN TRB Computer Instructor 2022 Model Question Paper | TN TRB Computer Instructor Previous Year Paper
TN TRB Tamil Nadu Teachers Recruitment Board have released soon the Hall Ticket for the recruitment of TN TRB Post Graduate Assistants / Physical Education Directors Grade – I and Computer Instructor Grade I Vacancies. TN TRB PG Assistant/PE Director and Computer Instructor Exam going to be conducted on 12.02.2022, 13.02.2022, 14.02.2022& & 15.02.2022. In this portal topic wise model paper published by us for the aspirants.
Von Neumann architecture is
(a) SISD
(b) SIMD
(c) MIMD
(d) MISD
In register addressing mode operands are looked at
(a) In cache
(b) In secondary storage
(c) In CPU
(d) In primary memory
The example of implied addressing is
(a) Stack addressing
(b) Immediate addressing
(c) Indirect addressing
(d) None of these
Normally digital computers are based on
(a) AND and OR gate
(b) NAND and NOR gate
(c) NOT gate
(d) None of these
ALU unit of a computer performs
(a) addition, substraction operations
(b) all types of arithmetic operations
(c) AND, OR and multiplication operations
(d) all arithmetic and logical operations
A CPU has 16 bit program counter. This means that the CPU can address
(a) 16 k memory locations
(b) 32 k memory locations
(c) 64 k memory locations
(d) 256 k memory locations
CPU consists of
(a) ALU, CU and registers
(b) ALU and CU
(c) ALU, CU and Hard Disk
(d) ALU, CU and Monitor
Cache memory resides in between
(a) CPU and RAM
(b) RAM and ROM
(c) CPU and Hard Disk
(d) None of these
The circuit used to store one bit of data is known as
(a) Encoder
(b) OR gate
(c) Flip-Flop
(d) Decoder
In computer, substraction is generally carried out by
(a) 9’s compliments
(b) 10’s compliments
(c) 1’s compliments
(d) 2’s compliments
Floating point representation is used to store
(a) Boolean values
(b) Whole numbers
(c) Real values
(d) Integers
The average time required to reach a particular storage location in memory and obtain its contents is called the
(a) seek time
(b) turnaround time
(c) access time
(d) transfer time
The address mode used in an instruction of the form ADD AX, [SI] is
(a) Absolute
(b) Indirect
(c) Index
(d) None of these
The idea of cache memory is based
(a) on locality of reference
(b) on 90-10 rule
(c) on cluster
(d) All of the above
In a memory mapped I/O system, which of the following will not be there ?
(a) LDA
(b) SUB
(c) ADD
(d) CMP
Leave a Reply