MCQ on Advance Microprocessor & Micro controller

Rajasthan Polytechnic Third Year Paper 2016 – Advance Microprocessor & Microcontroller

In case of Winchester disk, the head
(a) Contacts the recording surface occasionally
(b) Never contacts the disk surface
(c) Always contacts the recording surface
(d) Contacts only the landing area while not recording

Which one of the following does not generate a hardware interrupt?
(a) Printer
(b) Hard Disk
(c) Floppy Disk
(d) Program Error

Cache memory is implemented by using?
(a) Dynamic RAM
(b) EPRAM
(c) Sttic RAM
(d) EPROM

The instruction, MOV AX [2500h] is an example of
(a) Immediate addressing mode
(b) Direct addressing mode
(c) Indirect addressing mode
(d) Register addressing mode

The programmable interrupt controller is required to
(a) Handle one interrupt request
(b) handle one or more interrupt requests at a time
(c) handle one or more interrupt request with a delay
(d) handle no interrupt request

In 8255 device, a Register that receives or transmits data upon the execution of input or output instructions by the microprocessor is
(a) control word register
(b) read/write control logic
(c) 3-state bidirectional buffer
(d) None

When non-specific EOI command is issued to 8259a it will automatically
(a) set the ISR
(b) reset the ISR
(c) set the INR
(d) reset the INTR

In 8257 the pin that requests the access of bus to the system is
(a) HLDA
(b) HRQ
(c) ADSTB
(d) None of the mentioned

In 8253 Programmable Timer controller control word format, if RL1=1, RL0=1, then the operation performed is
(a) Read/load least significant byte only
(b) Read/load most significant byte only
(c) Read/load LSB first and the MSB
(d) Read/load MSB first and then LSB

Once the processor responds to an INTR signal, the IF flag is automatically
(a) Set
(b) Reset
(c) High
(d) Low