Objective questions on ARM Mircocontroller and system design

M.Sc Electronics Semester III Exam Oct/Nov 2019 Shivaji University Kolhapur

When clock frequency goes up in ARM microprocessor, dynamic power _____?
(a) increases
(b) decreases
(c) becomes zero
(d) doesn’t change

The Cache is placed between _____
(a) Flash memory and registers
(b) main memory and core
(c) Peripherals
(d) N one of these

What is the significance of “!” in a load/store instruction?
(a) Don’t update base register in post-indexed load/store
(b) Don’t update base register in pre-indexed load/store
(c) Update base register in post-indexed load/store
(d) Update base register in pre-indexed load/store

The addressing mode where the EA of the operand is the contentsof Rn is ____
(a) Pre-indexed mode
(b) Pre-indexed with write back mode
(c) Post-indexed mode
(d) None of the mentioned

The synonym of AMBA is _____
(a) ARM microcontroller Bus Architecture
(b) ARM Micro-bus architecture
(c) Advanced Microcotnroller Bus Architecture
(d) Advanced Micro-Bus Architecture

Pipelining stages of ARM include ______
(a) Fetch, Deconde, Write
(b) Fetch, Decode, Execute
(c) Fetch, Execute, Write
(d) Fetch, Decode Execute, Write

In LPC 2148, which among the following is/are the functions of Mask
(a) Byte addressability
(b) Relocation to ARM local bus for fastest possible I/O timing
(c) Treating sets of port bits in the form of group without changing other bits
(d) All of the above

Which of the following instructions are called Program Status Register transfer instructions?
(a) LDR, STR
(b) LDM, STM
(c) MCR, MRC
(d) MSR, MRS

In case of ARM LPC2148, I2C bus is ______
(a) bidirectional
(b) unidirectional
(c) omnidirectional
(d) all of these

The ARM processor executes _____ instruction set when T bit is set in CPSR register.
(a) ARM state
(b) Jazzel state
(c) thumb state
(d) None of these

The ____register is accessible in all processor mode
(a) link
(b) banked
(c) unbanked
(d) current program

In case of ARM LPC 2148, user mode is ____ mode
(a) privileged
(b) non-privileged
(c) both a & b
(d) None of these

When processor cannot decode an instruction ______ is used.
(a) Reset Vector
(b) Undefined instruction vector
(c) Data abort vector
(d) interrupt request vector

To more from an ARM register to a status register _____instruction is used
(a) MOV
(b) MRC
(c) MRS
(d) MSR