AP ECET Computer Science & Engineering Paper 2019
| Sr. No. | Question |
| 1 | Which among the following was the first version in the TTL family ?
(a) Standard (b) Low- Power (c) Schottky (d) Fast Ans –(a) |
| 2 | The logical sum of all the minterms of a Boolean function of n variables is
(a) 0 (b) 1 (c) N (d) n(n+1)/2 Ans –(b) |
| 3 | Circuits that generate the parity bit in the receiver and transmitter are called ______ and ______ respectively.
(a) Parity checker, Parity Generator (b) Parity Generator, Parity checker (c) Parity Generator, Parity encoder (d) Parity encoder, Parity decoder Ans –(a) |
| 4 | The characteristic equation for the complement output of a JK flip flop is
(a) Q’(t+1) = J’Q’+KQ (b) Q’(t+1)=J’Q’+KQ’ (c) Q’(t+1) = J’Q+KQ’ (d) Q’(t+1) = J’Q+K’Q’ Ans –(a) |
| 5 | If the register has both shifts and parallel load capabilities that is referred to as
(a) Universal shift register (b) Unidirectional shift register (c) Bidirectional shift register (d) Parallel shift register Ans – (a) |
| 6 | The capacity of a memory unit is usually stated as the total number of __________that it can store.
(a) Words (b) Bytes (c) Addresses (d) Bits Ans – (a) |
| 7 | Which among the following offers shorter read and write cycles ?
(a) Fast RAM (b) Commercial RAM (c) Static RAM (d) Dynamic RAM Ans – (c) |
| 8 | 4-to-16 line decoder can be constructed with ____2-to-4 line decoders with enable.
(a) 4 (b) 2 (c) 5 (d) 8 Ans – (c) |
| 9 | Which of the following registers of 8086 can also be used for memory addressing when data is transferred between I/O port and memory using certain I/O instructions?
(a) AX (b) BX (c) CX (d) DX Ans – (d) |
| 10 | In ___________addressing mode the operand is specified in the instruction itself.
(a) Implicit (b) Immediate (c) Direct memory (d) Displacement Ans – (b) |
| 11 | The intervals of no bus activity that occur between bus cycles are known as ________ state.
(a) Idle (b) Busy (c) Wait (d) Ready Ans –(a) |
| 12 | __________register of 8086 can be used for I/O operations and string manipulation.
(a) Count (b) Data (c) Accumulator (d) Base Ans – (c) |
| 13 | Which among the following processor has a built in math-co-processor in a single chip.
(a) 80186 (b) 80286 (c) 80386 (d) 80486 Ans – (d) |
| 14 | _________instruction copies the contents of AH to lower byte of flag register of 8086.
(a) LAHF (b) SAHF (c) PUSHF (d) POPF Ans – (b) |
| 15 | The flag of 8086 that is NOT affected by the instruction INC Scr is ________
(a) AF (b) SF (c) CF (d) ZF Ans – (c) |
Leave a Reply