M.Sc Electronics Semester III Exam Oct/Nov 2019 Shivaji University Kolhapur
As temperature increases carrier mobility _____
(a) remains constant
(b) increases
(c) decreases
(d) None of these
In polysilicon interconnect _______ is used as gate material.
(a) Silicon
(b) silicide
(c) Tantalum
(d) All of these
Fall time is the time for a waveform to fall from _____ of its steady state value.
(a) 90% to 10%
(b) 100% to 10%
(c) 100% to 50%
(d) 50% to 10%
The most popular algorithm level environment is _____
(a) PMS
(b) Pseudo-layout
(c) Flowcharting
(d) schematic
Absolute value of threshold voltage decreases with an ____ in temperature.
(a) Decreases
(b) increases
(c) Constant
(d) None of these
In PMS design environment P Stands for ______
(a) Parameter
(b) progress
(c) process
(d) Processor
The cell at the bottom of the hierarchy is called as _____
(a) root cell
(b) leaf cell
(c) composition cell
(d) all of these
The basic raw material used in CMOS fabrication is _____
(a) disk of silicon
(b) wafer of silicon
(c) both a and b
(d) ingots of silicon
In standard cell based design ____ process connects the modules with wires
(a) placement
(b) floor planning
(c) routing
(d) None of these
Latchup result in ____
(a) power down of circuit
(b) failure of circuit
(c) parasitic effect
(d) all of these
Material used for local interconnect layer is _____
(a) polysilicon
(b) single crystal silicon
(c) sapphire
(d) silicide
N-well CMOS process start with lightly dopped _____
(a) n-type substrate
(b) p type substrate
(c) sapphire layer
(d) polysilicon layer
In VLSI design components of design are commonly called as -___
(a) cells
(b) tools
(c) footprints
(d) constraints
Which of the following does affect the circuit’s behavior?
(a) temperature
(b) supply voltage
(c) both a and b
(d) design tools
Leave a Reply